1. Field of the Invention
The present invention relates to a timing adjusting circuit and semiconductor memory device having a ferroelectric capacitor.
2. Description of the Related Art
A ferroelectric memory device is conventionally known as a semiconductor memory device which has memory cells using ferroelectric capacitors and stores data in accordance with the direction of polarization of the ferroelectric capacitors. The ferroelectric capacitor decreases the polarization amount (depolarization) by repeating polarization reversal. The hysteresis characteristic transition takes place from the curve indicated by the solid line in FIG. 8 to the curve indicated by the broken line. For example, when polarization reversal from Vcc=−V1 in FIG. 8 occurs, and Vcc=0 V transition (decrease) from a charge Q1 to a charge Q2 takes place. That is, the ferroelectric capacitor increases its capacitance during polarization reversal due to a change over time ((Q3−Q1)/V1<(Q3−Q2)/V1 in FIG. 8).
The schematic arrangement of a conventional ferroelectric memory device having memory cells formed from ferroelectric capacitors will be described next.
FIG. 9 is a block diagram showing the schematic arrangement of a conventional ferroelectric memory device. Referring to FIG. 9, a ferroelectric memory device 101 has memory cells formed from ferroelectric capacitors and stores data in accordance with the direction of polarization of the ferroelectric capacitors. A row decoder 103 selects a word line on the basis of externally input address data. In a memory cell array 102, memory cells formed from ferroelectric capacitors (to be described below) are arranged in an array.
In accordance with data stored in the memory cells, a sense amplifier circuit (S/A circuit) 104 amplifies the potential of a bit line selected by a column decoder 105 (to be described later). The column decoder 105 selects a bit line on the basis of externally input address data. The column decoder 105 also outputs an activation signal that activates the sense amplifier circuit 104.
An input/output data processing circuit 106 latches or buffers input data to be stored in the memory cell array 102 or output data read out from the memory cell array 102, thereby inputting/outputting data from/to an external device through an input/output data bus. A control circuit 107 controls the operations of the above-described circuits on the basis of a control signal. With the above arrangement, the ferroelectric memory device 101 executes processing of writing/reading data in/from memory cells at portions designated by address data.
The schematic arrangement of a memory cell formed from ferroelectric capacitors will be described next. FIG. 10 is a view showing the schematic arrangement of a conventional memory cell formed from ferroelectric capacitors. Referring to FIG. 10, a memory cell M has ferroelectric capacitors C1 and C2 and transistors Tr1 and Tr2. One terminal of each of the ferroelectric capacitors C1 and C2 is connected to a corresponding one of bit lines BL and /BL through the transistor Tr1 or Tr2. The other terminal of each of the ferroelectric capacitors C1 and C2 is connected to a plate line PL. The bit lines BL and /BL are connected to the sense amplifier circuit 104. With this arrangement, when the sense amplifier circuit 104 is activated, it precharges the bit lines BL and /BL or amplifies the potential difference between the bit line BL and the bit line/BL. The gate terminals of the transistors Tr1 and Tr2 are connected to a word line WL. The transistors Tr1 and Tr2 are turned on/off by controlling the word line WL.
The influence of an increase in capacitances of the ferroelectric capacitors C1 and C2 due to a degradation over time shown in FIG. 8 in data read operation from the above-described memory cell M will be described with reference to an accompanying drawing. FIG. 11 is a timing chart showing the influence of an increase in capacitances of the ferroelectric capacitors C1 and C2 due to a degradation over time in data read operation from the above-described memory cell M shown in FIG. 10. As shown in FIG. 11, when the capacitances of the ferroelectric capacitors C1 and C2 increase, data output to the bit lines BL and /BL becomes slower, as indicated by broken lines in FIG. 11. To cope with this, the activation timing of the sense amplifier circuit 104 that amplifies the potential difference between the bit line BL and bit line/BL must be delayed from t1 to t2.
However, the progress of the above-described degradation in ferroelectric capacitors over time varies between the memory cells because it depends on the number of times of repetition of polarization reversal. For this reason, if the activation timing of the sense amplifier circuit is uniformly delayed, the data output timing is unnecessarily delayed.
Especially, when a plurality of sense amplifier circuits are used, it is difficult to appropriately adjust the activation timing of each sense amplifier circuit in accordance with a change over time.
Additionally, generally speaking, the above-described problem in the field of electric circuits, it is difficult to adjust the timing in accordance with a change in circuit element over time.